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This white paper is also available in pdf
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DPECL White Paper
The following is a White Paper explaining the design methodology for low jitter, low emission timing solutions.
- The Challenges of High Speed Digital Clock Design
- Design Methodology
- PECL Advantage
- Design Subtleties
The Challenges of High Speed Digital Clock Design
Designing clock generation and distribution systems for today's high speed digital electronic devices poses numerous challenges to the design community. At higher speeds, transmission lines and their components behave differently than they do at lower speeds, generating such signal integrity problems as jitter, noise, reflections, and crosstalk if not properly specified and configured. Therefore, when designers approach a project that will have a high speed digital application, they must factor in a variety of signal integrity provisions that are not necessary in lower speed applications.
Key challenges of planning a high speed digital project include:
Minimizing timing jitter. It is critical for
high speed, high frequency electronics to have low timing jitter. Poor
jitter characteristics not only affect data error, but also could cause
failures in phase lock loops using this source as a reference. If the
source is to be used as a display clock reference, the result will be
a blurry display. As a rule, the faster the signal moves through the transition
region, the less system jitter will be produced (see image below).
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| In high speed applications, the faster the signal
moves through the transition region, the less jitter will be produced. |
Reducing emissions. In high speed applications, the likelihood of
generating electromagnetic interference (EMI) increases dramatically.
FCC regulations regarding EMI noise reduction are becoming more stringent
with faster digital speeds. Designers need to address such characteristics
as transmission lines, differential signals, signal amplitude, and harmonic
content in order to maximize the energy that will be delivered to the
load, thus reducing the amount of energy emissions.
Ensuring stability. In general, the higher the specified operating frequency of the electronic system you are designing for, the more critical the clock stability is. Unstable clock performance can cause an increased bit error rate, erroneous data, or missed data in digital systems, whether they are local or wide area systems.
Transmission line impedance matching. The impedance and length of the entire transmission line must be measured and matched with each termination. If impedance matching is overlooked, emissions, crosstalk, and reflections can occur.
Power supply considerations. The prime consideration here is to make sure that the clock is noise-free. Low power supply consumption requirements are also increasing with today's higher speed systems.
The key to achieving optimum system performance in a high speed application starts with an effective design methodology for clock generation and distribution. Put simply, the designer should adopt a methodology that addresses the various clock generation and distribution components as a complete solution, not as individual parts. Careful attention to the selection of the appropriate components and circuit distribution method should be given at the outset of the project, keeping in mind the interrelation of the components to one another. Further, it is important to consider the characteristic impedance of all active and passive components at the frequency of operation as the design progresses.
Proper selection of the following clock generation and distribution components is essential:
- The crystal oscillator and its output logic
- The clock driver, which in some cases will contain enable functions
- Translators to CMOS at 5V or 3V supply
- The transmission line (twisted pair, coax, PCB traces)