DPECL White Paper

Design Methodology

An effective methodology for achieving optimum system performance addresses the various clock generation and distribution components as a complete solution. Careful selection of the appropriate components should take place at the outset of the project, keeping in mind the components' interrelation to one another.

1 Crystal Oscillator and Logic Selection

Selecting the appropriate crystal oscillator is of the utmost importance in a high speed application, since it will provide the clock reference for the entire clock distribution system.

Stringent crystal oscillator applications typically require a frequency stability of ±20 ppm, fast rise and fall times of less than 600 picoseconds, low characteristic jitter, and a Positive Emitter Coupled Logic (PECL) differential output. The frequency stability will provide a reliable system reference, while fast rise and fall times of the waveform will result in low system jitter. (Although saturating the transition with fast rise and fall times can introduce unwanted noise, this noise will be canceled out by the use of differential signals.)

Logic Selection: PECL Advantages Using a PECL logic output provides critical advantages over CMOS logic output technology in high speed applications. Unlike CMOS technology, PECL technology features a differential output, which is essential for reducing emissions. Yet, like CMOS, PECL obtains its operating power from a positive power supply (rather than the negative power supply voltage that powers ECL logic technology), enabling the necessary compatibility with CMOS logic interfaces at the load points.

In addition, PECL technology allows voltage compensation for further rejection of noise on the positive voltage supply. All modern PECL devices contain on-chip bandgap regulators that provide voltage compensation for noise margins with variations in the supply voltage, as well as in junction and ambient temperatures. Because PECL circuits consist of supply-regulated current sources which are switched via steering logic to load resistors, the designer benefits in two ways:

1) the supply current remains unchanged with operating frequency

2) AC performance remains unchanged with voltage, temperature, and frequency

Residual sensitivities of less than 1mV/V for levels, threshold and noise margins with respect to supply voltage may be achieved.

For junction temperatures, residual sensitivities of less than 0.1mV/C are achieved for the same parameters.

Crystal Oscillator Quality In addition to ensuring low jitter in the waveform, designers should be sure that jitter is minimized in the oscillator itself. This is achieved by selecting an oscillator containing a very high Q crystal. Further, the crystal should be tuned to the oscillator circuit for optimization by the oscillator manufacturer. Use of a PLL synthesizer in the oscillator design should be avoided, since jitter is created by the noise in the phase lock loop.

Other Oscillator Considerations In PECL systems, all oscillator circuits should have the power supply well decoupled at the oscillator. PECL devices need to have this addressed aggressively, since PECL is referenced only to the most positive side of the power supply. Thus, for PECL the Vcc needs to be as noise-free as possible. Because oscillator characteristics do change with load impedance and load bias voltage, it is important to specify the actual load being used and communicate this to the oscillator vendor.

The chosen oscillator should have a tight symmetry of at least 45% minimum and 55% maximum, and should produce repeatable waveforms to ensure signal consistency. A ground plane should be used (see Design Subtleties page).

2 Clock Driver/Distribution Considerations

The clock driver should be a PECL differential device -- with differential inputs to receive the oscillator signals, and differential outputs to distribute the signals on the PCB. If clock gating is desired, there should be an Enable pin, probably single ended.

Another aspect of clock driving should be structural symmetry of the device, which will reflect in better overall signal integrity.

Regeneration buffering may be required when trace length and/or attenuation demand it. It is important to structure regeneration such that received signals have settled out and are not still on their rising or falling edge. Otherwise further attenuation may be generated rather than signal buffering.

3 Translator Requirements

If CMOS is to be driven, PECL-to-CMOS conversions will be needed. A dedicated translator should be used for each application-specific point. It is important to locate each translator as close to the load point as possible in order to maintain good signal integrity.

4 Transmission Line Considerations

For any high speed and high frequency clock distribution system, properly configured and terminated transmission lines are a requirement. Following are some of the basic characteristics required for a good transmission line.

• The source, transmission line, and load impedances need to match as closely as possible to minimize losses in the transmission line.
• The transmission line should be free of discontinuities which can cause poor performance.
• The transmission line should not have stubs or branches which can result in poor performance.
• The load must be at the opposite end of the transmission line from the source.
• The source must be capable of driving the transmission line impedance.

Differential Schemes A differential transmission scheme should be adopted which makes use of the differential nature of both the output of PECL drivers and the input of PECL receivers.

The differentially transmitted signals will have a very large common mode rejection range (to capacitively and inductively coupled noise signals) and will be insensitive to supply voltage and temperature variations. The resulting transmission system will be quite immune to external noise sources, and will therefore minimize emissions.

Termination and Layout Proper terminations are necessary to maximize power transfer while preventing signal reflections (bouncebacks) and noise.

Termination methods cause an undue amount of confusion. The following tips can help avoid confusion and will help meet the requirements of complex digital systems.

1. Print the highest impedance level line that can be manufactured on the PCB with reasonable repeatability. Usually this will be 100 ohms, require and it will reduce the power demand for termination, if compared to a 50 ohm scheme, by a factor of two.
   
   
2. If group delay is a concern, run the two traces on the top of the PCB, or within the PCB (propagation delay is a function of dielectric constant).



3. The width between each output trace should be five times the width of each trace, in order to minimize crosstalk. Route the traces directly to the various tap points--stubs should be avoided, since they generate noise. If the tap point is a translator to CMOS, place it as close as is practical to the CMOS logic to be driven.



4. Each termination should be built as a source-terminated input to the transmission line or the destination--termination should be structured as the Thevenin equivalent of the characteristic line impedance (50-100 ohms). Either method requires two resistors as a termination but eliminates the need for termination supply voltage (and its distribution plane).



5. At 3.3V, the termination may be a single 100 ohm resistor to ground, if 100 ohms lines are used.

Resistor Considerations A distinction should be made between pull-down resistors, which simply provide a load current for the open emitter follower, and termination resistors.

For very short connections of low parasitic capacitance, 2 kohms to GND may be practical. If, however, a longer distance must be bridged by the interconnect, this interconnect will have to be terminated by its characteristic impedance in order to maximize power transfer and minimize reflections. The characteristic impedance of such interconnects generally lies between 40 and 120 ohms.

Given this range and the output drive capability of the emitter followers, the termination resistor can also serve the purpose of the pull-down resistor, but in several termination schemes, they are indeed kept as separate components.

Conclusion

The latest generation of high speed digital systems demand better signal integrity. By using the techniques covered in this design methodology, designers will greatly reduce system jitter, emissions, noise generation, and crosstalk.

The primary steps to success are to utilize a PECL differential output logic clock oscillator that provides fast signal transitions; a PECL differential clock driver; dedicated PECL-to-CMOS translators for each load point; and impedance matched and properly terminated transmission lines.

To support this methodology, it is helpful to choose component manufacturers who will work with you, and with one another, in the shared goal of providing a complete solution. The result will be faster time-to-market, better product quality, and improved ability to pass EMI testing requirements.